Computer graphics applications are becoming increasingly complex. The large amount of data a computer processes when running a program having complex graphics slows down the computer. Computer graphics software cannot reduce the amount of data to be processed, and therefore cannot solve the problem of speeding up the graphics processing. Thus, some computer engineers have improved computer graphics memory architectures to improve graphics processing speed while accessing data to the graphics memory.
FIG. 1 depicts a conventional computer system 10. The computer system 10 has a processor 12 comprising of one or more CPUs, a main memory 14, a disk memory 16, and an input device 18, such as a keyboard and mouse. These devices 12-18 are connected to a bus 20 which transfers data, i.e., instructions and information, between the devices 12-18. A graphics controller 30 is also connected to the bus 20. As shown, the graphics controller 30 includes a drawing processor 32. The drawing processor 32 is also connected to an address generator 36 and a data input of a frame buffer 34 and a Z buffer 35. The address generator 36, in turn, is connected to RAS (row address select) (not shown), CAS (column address select) (not shown), and chip select inputs (not shown) of the frame buffer 34 and Z buffer 35. Illustratively, the frame and Z buffers 34, 35 are implemented with plural VRAMs (video random access memories). The frame buffer 34 is connected to a display device 38, such as a cathode ray tube (CRT) or liquid crystal display (LCD) monitor.
The drawing processor 32 receives instructions from the processor 12 for drawing objects. For instance, in the case of a computer aided design (CAD) application, the processor 12 may receive user input regarding creating and locating objects in three dimensional (3-D) space. The processor 12, in turn, transfers instructions regarding the size, location, texture, translucence, etc. of such objects to the drawing processor 32. In response, the drawing processor 32 creates a pixel image representation of a plane of view of such objects in 3-D space. The pixels of the image of each plane of view form part of a frame that is stored by the drawing processor 32 in the frame buffer 34. In 3-D graphics applications, each pixel has color data (e.g., data for the red, green, and blue values of the pixel), and so called Z-values, relating to the Z-coordinate, or depth, of a graphical image. The pixel color data is stored in the frame buffer 34. The pixel Z-values are stored in the Z buffer 35. In two dimensional (2-D) applications, the Z-buffer 35 may be used as an additional frame buffer to hold pixel color data. Drawing processors 32 are known, such as is disclosed in U.S. Pat. Nos. 5,046,023 and 5,185,856. The latter reference discloses a drawing processor that is specifically adapted for rendering 3-D objects. The contents of these patents are incorporated herein by reference.
FIG. 2 is a block diagram of one type of known computer graphics memory architecture. The architecture comprises a drawing processor 32', a frame buffer 34, a Z buffer 35, and a data path 40. The drawing processor 32' comprises a 3-D processing unit 42' and a 2-D processing unit 44'. The 3-D processing unit has a pixel color processor C and a pixel Z-value processor Z. All of these hardware elements are well known to those skilled in the art. This hardware is disclosed, for example, in the patents discussed above.
In a 3-D application, the frame buffer 34 holds color data for a number of pixels, each pixel having 32 bits of color data. In the architecture of FIG. 2, the frame buffer 34 is 64 bits wide and is connected to a 64 line data path 40. The data path 40 can handle two pixels of color data simultaneously when data is transported from the buffers to the drawing processor or returned to the buffers after processing. The Z buffer 35 holds Z-value data for a number of pixels, each pixel having 24 bits of Z-value data. The Z buffer is 64 bits wide and is also connected to a 64 line data path 40. The 16 bit difference between the number of Z bits and the available data lines cannot be avoided because the data path 40 is 64 lines. In any event, these 16 data lines are used when the Z buffer 35 is used as an additional frame buffer during 2-D applications discussed below. Thus, the data path 40 can handle two pixels of Z-value simultaneously.
For each input or output (I/O) transaction between one of the buffers 34, 35 and the drawing processor 32', either two pixels of color or Z-value data may be retrieved from or written into the appropriate buffer. Because two pixels of either color or Z-value data are being processed at the same time, the drawing processor 32' has two copies of the color processing hardware C (this is represented in FIG. 2 by the indication 2.times.C) and two copies of the Z processing hardware Z (represented by 2.times.Z). For 3-D applications this architecture requires 64+48=112 data lines. This memory architecture uses 112 data lines, two 3-D color processors, and two 3-D Z-value processors to process two pixels of data (e.g., two pixels of color or two pixels of Z-values) per I/O transaction.
In the 2-D application, two pixels of color data may be retrieved from either the frame buffer 34 or the Z buffer 35 and brought to the 2-D processing unit 44'. Because two pixels are processed at once, the drawing processor 32' requires two copies of the 2-D color processing hardware. Thus, 64 data lines are required to process the 2-D application.
Overall, this memory architecture uses 112+64=176 total data lines to process graphics information. Although this is a very large memory architecture, it processes two pixels of color or Z-value data (e.g., 64 bits) in a single I/O transaction.
FIG. 3 is a block diagram of another type of known computer graphics memory architecture. This architecture comprises a drawing processor 32", a frame buffer 34, a Z buffer 35, and two data paths 48, 50. The drawing processor 32"comprises a 3-D processing unit 42"and a 2-D processing unit 44". The 3-D processing unit has a color processor C and a Z-value processor Z.
As in FIG. 2, this hardware is well-known to those skilled in the art. The frame buffer 34 holds 32 bit pixel color data for a number or pixels. The frame buffer 34 is 32 bits wide and is connected to a 32 bit line path 48. In a 3-D application, the 32 line data path 48 transports the color pixel data to the 3-D processor color processing unit C. The Z buffer 35 holds a number of 24 bit Z-values. The Z buffer is 24 bits wide and is connected to a 24 line data path 50, which path transports the Z-value data to and from the 3-D processor Z-value processor Z.
In this architecture, only one pixel of color or Z-value data is processed per I/O transaction. Therefore, only one copy of the 3-D color and Z-value processing hardware are used. For 3-D processing, there are 32+24=56 total data lines. This memory architecture uses 56 data lines, one 3-D color processor, and one 3-D Z-value processor to process one pixel of 3-D color or one pixel of 3-D Z-value information per I/O transaction. Although this architecture is smaller and less expensive to manufacture than the FIG. 2 architecture, it processes one pixel of color or Z-value data per I/O transaction. Thus, it processes graphic information at half the speed of the FIG. 2 architecture. The 24 bit Z buffer is not used in 2-D applications. Overall, this memory architecture uses 56+32=88 total data lines to process graphics information.
FIG. 4 is a block diagram of a computer graphics memory architecture 100 according to the invention described in related patent application Ser. No. 08/531,600 ("the '600 invention"). This preferred embodiment has a frame buffer 134, a Z buffer 135, a data path 140, and a drawing processor 132. The frame buffer 134 has two parts, a "forward" (even) part 151 and a "reverse" (odd) part 152. The Z buffer also has a "forward" (even) part 161 and a "reverse" (odd) part 162. The drawing processor 132 has a 3-D processor 142 and a 2-D processor 144. The 3-D processor 142 has a first reversing switch, such as a first multiplexer circuit, 150 connected to an input of the 3-D color processor C, and Z-value processor Z. A second reversing switch, such as a second multiplexer circuit, 154 is connected to an output of the color and Z processors. A "forward/reverse" circuit 156 activates the first and second reversing switches or multiplexer circuits 150, 154. The 2-D processor 144 has a third reversing switch, such as a third multiplexer circuit, 158 connected an input of the 2-D processor. A fourth reversing switch, such as a fourth multiplexer circuit, 160 is connected to an output of the 2-D processor. A "frame buffer/Z buffer" circuit 162 activates the third and fourth reversing switches or multiplexer circuits 158, 160.
In 3-D applications, the frame buffer 134 holds pixel color data in a buffer 134 wide enough to connect at least two pixels of data to the data path 140. In a preferred embodiment, the frame buffer is 64 bits wide. The Z buffer holds Z-value data in a buffer 135 wide enough to connect simultaneously at least two pixels of data to the data path 140, and preferably is wide enough to connect two pixels of color data to the data path 140. In a preferred embodiment, the Z buffer is 64 bits wide. Both buffers are connected to a data path 140 which transmits the data to and from the drawing processor 132. In a preferred embodiment, the data path 140 has 64 lines.
The frame buffer forward (even) part 151 holds pixel color data, which data is referred to as Ca, and connects at least one pixel of data to a first set of data path 140 lines. Preferably, the frame buffer forward (even) part 151 connects to data path 140 lines 0-31. The frame buffer second portion 152 holds pixel color data, which data is referred to as Cb, and connects at least one pixel of data to a second set of data path 140 lines. Preferably, the frame buffer reverse (odd) part 161 connects to data path 140 lines 32-63. The Z buffer forward (even) portion 161 holds 3-D Z-value data, referred to as Za, and connects at least one pixel of data to the second set of data path 140 lines. Preferably, the Z buffer forward (even) part 161 connects to data path 140 lines 32-63. The Z buffer reverse (odd) portion 162 holds 3-D Z-value data, referred to as Zb, and connects at least one pixel of data to the first set of data path 140 lines. Preferably, the Z buffer reverse (odd) part 162 connects to data path 140 lines 0-31.
In this preferred embodiment, either two 2-D pixels or one complete 3-D pixel--both color and Z-value--are processed in a single I/O transaction. Two copies of 2-D processing hardware are preferably provided, but only one copy of the 3-D color and Z-value processing hardware is preferably provided. The 2-D application uses 64 data lines; the 3-D application uses a total of 32+24=56 data lines. For the preferred embodiment of the '600 invention, a total of 64+56=120 lines are used. A table comparing the number of data lines used by the prior art architecture and a preferred embodiment of the '600 invention is set out below:
______________________________________ FIG. 2 FIG. 3 '600 Invention ______________________________________ Lines used in 2-D 64 32 64 Lines used in 3-D 64 + 48 = 112 32 + 24 = 56 32 + 24 = 56 Total Lines 176 88 120 ______________________________________
A table comparing the processing speeds of the prior art architectures and the '600 invention are set out below:
______________________________________ FIG. 2 FIG. 3 '600 Invention ______________________________________ 2-D processing speed 2 pixels per 1 pixel per I/O 2 pixels per I/O I/O 3-D processing speed 2 color or 2 1 color or 1 1 pixel color Z-values per Z-value per I/O and Z-value per I/O I/O ______________________________________
Thus, the processing speed of the '600 invention is equivalent to the speed of the architecture shown in FIG. 2. Both process 64 bits in one I/O transaction. However, this equivalent speed is performed by the '600 invention with much less hardware, and therefore is smaller and less expensive to implement. For 3-D applications, the '600 invention processes at twice the speed as the architecture shown in FIG. 3 and has the same amount of hardware.
Although the invention described in the '600 invention has many advantages over the prior art, it has several shortcomings. First, two independent buffers are provided: the frame buffer 134 and the Z buffer 135. Each of these buffers is further divided into two parts, the forward (or even) part 151, 161 and a reverse (or odd) part 152, 162. Each portion of each buffer is connected to particular bit lines of the databus. As a result, the databus arrangement and control circuits take up a relatively large area. Second, the double buffer design of the preferred embodiment uses 4 megabytes of memory. Thus, when increasing the memory size, expansion is made in 4 Mb increments. Third, a circuit board containing the preferred embodiment of the device described in the '600 invention uses two expansion slots. This uses a large amount of circuit board area and may reduce the flexibility of the device.
It is an object of the present invention to provide an improved computer graphics memory which has the many advantages of the device described in the '600 invention yet overcomes these several shortcomings.